Ernest Levine

Ernest Levine

Ph.D.
Ernest Levine
Professor of Nanoscience

Contact

Phone Number:
518-437-8623
Office Address:
CESTM
B230E
Location
Albany
Faculty/Staff
Faculty
Department
Nanoscience
College
College of Nanoscale Science + Engineering
A button to see Dr. Ernest Levine Discuss Nanoscience at  SUNY Poly CNSE
Dr. Ernest Levine Discusses Nanoscience at 
SUNY Poly CNSE


Watch Professor Levine's "Inside CNSE" video interview on his Integrated Circuit Fabrication and Yield Control course

Degrees

  • Ph.D. (Material Science) 1965, New York University, Bronx, NY
  • B. Met. Eng. (Metallurgical Eng.) 1959, RPI, Troy, NY

Areas of Research

  • low k BEOL
  • Cu BEOL
  • electromigration
  • thermal voids
  • reliability of interconnects

Research Description

Professor Levine has conducted over 25 years of research centered upon all areas of interconnect integration and reliability of back end of the line for integrated circuit chips. He has done extensive work on the construction of chips, integration using new low k materials, and understanding of the role of microstructure in controlling properties of back end of the line interconnect build structures such as vias. Levine has also examined time-dependent fail mechanisms and electromigration-related structural problems in copper and aluminum, W stud technology, and Hillock formation as related to constraint and structural properties. Levine is a known expert in process control and yield control problems and methodologies.

Partial List of Publications

E. Levine and J. Kitcher
Electromigration Damage in Interconnects
IEEE Reliability Symposium (1980)

E. Levine and J. Kitcher
Electromigration Damage with Ti Underlay and Overlay
VMIC conference proceedings (1991)

E. Levine and J. Kitcher
Thermal and Electromigration Voiding
Amer. Vacuum Society, Vol 13, Cornell symposium (1992)

T. Bartush and E. Levine
A Four Level VLSI Bipolar Metalization Chip
IBM Journal of R&D V36 (1992)

Ed Barth and E. Levine
Integration of Cu and Fluorosilicate Glass in .18 micron Technology
IEEE 2000 Interconnect Proceedings (2000)

E. Levine and G. Thomas
Application of Kikuchi Maps
Journal of Applied Physics 37-(1966).

J. Gambino and E. Levine
Effect of Contact Implants on Patterning of W Studs
Materials Research Society (1996)

J. Petrus, B. Engel, and Levine
The SEM Lab - From Sample Input to Final Preparation
EDFAS Supplement, p 19-33 (2001)

Stress Voiding in Copper Interconnect Lines
Stress Migration Symposium 2002

The Art of Sample Preparation for Failure Analysis Laboratories
EDFAS Supplement (2004)

Invited Seminars/Outside Activities

Workforce education is a primary goal of Professor Levine's work. To that end, he is often invited to speak nationally and internationally:

  • Multiple invited two-day seminars on IC Fabrication to numerous companies such as IBM, AMD, Infineon, MKS Instruments, AZ, Zygo Corp., KLA, Air Products, Shipley, Rodel and LAM
  • Two day IC Fabrication seminars sponsored by Solid State Technology at University at Albany
  • Editorial advisor to Solid State Technology Magazine

Research Interests and Background

Understanding of the role of microstructure in controlling properties of back end of the line interconnect build structures such as vias. Control of Via Resistance as a function of build level and reliability stressing. Role of barrier films in controlling via R and fill properties. Stress voids and hillocks, time dependent fail mechanisms and electromigration related structural problems in Copper and Aluminum W stud technology. Hillock formation as related to constraint and structural properties. Problems in low k back end of the line insulator integration including cmp, size dependence and etch interactions with insulator. Process control and yield control problems and methodologies.

Awards

  • Multiple IBM industrial division awards for outstanding contributions to progress
  • Multiple IBM awards for outstanding achievements in research

Patents

Diverse patent portfolio in back end of the line chip construction. Over 20 patents. Representative patent areas include:

  • Under and over Ti metallurgy for electromigration improvement used by nearly all companies using Al metallurgy - multiple awards at IBM for this patent
  • Use of triple guard rings for protection of chips against humidity incursions - used in chips being built for use in today's market
  • Improved process for depositing barrier liners in Cu damascene
  • Improved fatigue life of solder balls in C4 construction through use of spacers
  • New back end of the line insulator with spin on dilelectric

 

 

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