The Center of Excellence in Nanoelectronics and Nanotechnology at SUNY Polytechnic Institute's Colleges of Nanoscale Science and Engineering is the location for the global headquarters and operations of SUNY Poly SEMATECH, a 12-member global consortium of major computer chip manufacturers.

SUNY Poly SEMATECH coordinates and oversees next-generation research, development and commercialization programs in lithography, interconnects, and metrology, among others, while managing global reach and influence through various program partnerships around the world in emerging nanotechnology-driven applications such as nanobiotechnology and sustainable energy.

SUNY Poly SEMATECH hosts and administers over 12 centers and consortia, including the EUV Resist Test Center, EUV Mask Blank Development Center, EUV Process Development Center, Alternative Lithography Technologies Center, 3D Interconnect Center, Advanced Metrology Center, the Universal Nanoelectronics Institute for Technology and Education, and the New York Alliance for Advanced Science and Technology. Examples of technical programs include: SEMATECH first took root at SUNY Poly in 2002, with the establishment of a $400-million, next-generation 300mm R&D center at SUNY Poly's Albany NanoTech complex. To support the program, New York State contributed substantial funding along with SEMATECH and its member companies, including IBM, with initial project research aimed at R&D in the area of advanced lithography infrastructure for extreme ultraviolet (EUV) lithography, which is crucial for computer chip manufacturing technology in the future because technical advances are expected to cause present day manufacturing methods to become obsolete for the most advanced chips.                         

  • 193i: Assess extensibility of immersion beyond 45 nm half-pitch, by improving fluids, lens materials, and resists.
  • EUV: Prepare EUV infrastructure for insertion at 32 nm half-pitch technology generation, using new micro-exposure and full field tools at resist test centers; work toward defect-free mask blanks.
  • 3D: Pursue wafer-to-wafer and die-to-wafer integration by roadmapping technology options, developing unit processes and metrology, and demonstrating functionality and reliability.
  • Metrology: Focus on the invention, research, development, and application of measurement methods for advanced technologies, with expanded programs in advanced microscopy, and metrology for CMOS and nanotechnology applications.

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