Joseph A. Piccirillo

Joseph A. Piccirillo

Joseph A. Piccirillo
Assistant Vice President for Module Engineering

Contact

Phone Number:
518-956-7146
Office Address:
NFX
449
Location
Albany
Faculty/Staff
Staff

Professional Background

  • Process Development Engineering Manager, College of Nanoscale Science and Engineering, University at Albany
  • Director of Site Operations - Applied Materials Inc., College of Nanoscale Science and Engineering, Albany, NY. 2005 - 2009 
  • Director of Engineering / Account Technologist - Applied Materials Inc. IBM Account Office, Fishkill, NY. 2002 - 2004
  • Director of Technology and Marketing Strategy - Applied Materials Inc. North America Accounts, Santa Clara, CA. 1998 - 2001
  • Rapid Thermal Anneal (RTP) Research Engineer - Applied Materials Inc. Kilby Research Labs, Dallas, TX. 1996 - 1998 
  • FEOL BiCMOS Integration Engineer - IBM Microelectronics Division, Essex Junction, VT. 1989 - 1995
  • Researcher: FEOL Logic CMOS Process Technology Development - IBM Microelectronics Division, Essex Junction, VT. 1981 - 1988

Education

  • BS Electrical Engineering, Binghamton University 1981

Various Additional Education

  • Quantum physics courses, Semiconductor device physic theory, University of Vermont 1987-1989
  • Managing in a complex environment: Semiconductor Fabrication, Austin TX, 1998 (two week course) 
  • Applied Materials Executive Leadership Program, UC Berkeley, Hass School of Business 2003 (six week course)

Responsibilities

As CNSE Process Development Engineering Manager, Mr. Piccirillo is responsible for providing process baseline and advanced technology development management necessary to support a diverse customer base portfolio. His development team contains the full complement of process capability, equipment knowledge and industry experience to provide diverse solutions in technology areas critical to the semiconductor industry.

The process development team maintains collaboration with key development partners - representing chip manufacturers, equipment suppliers, materials suppliers and many others - to advance CNSE's core technologies. As Engineering Manager, Joe works closely with the CNSE Integration and Operations teams to provide and improve FEOL, BEOL, MIM capacitor, FinFET, Nanowire and other module element offerings at the 32/22nm technology nodes.

Relevant Publications, Conference and Patents

  • "Investigation of Wet Etch of Sub-nm LaOx Capping Layers for CMOS Applications" 2010 Materials Research Society Conference
  • Patent: "Methods For Fabricating Dual Material Gate In A Semiconductor Device" 2009 US7,635,648
  • Invited Paper: "Ionized-PVD Stacked Barrier Structure of TaN/TaRu for 32nm BEOL Integration" 2008 Advanced Metallization Conference 
  • "Nitrided Gate Oxides for 3.3V Logic Applications: Reliability and Device Design Considerations" 1999 IBM Journal of Research and Development, Voume:43, Issue:3 
  • "Nitrogen Profile Engineering In Thin Gate" 1998 Materials Research Society Proceedings Symposium W, Volume: 525
  • "Selective Oxidation of Si in the Presence of W and WN" 1998 Materials Research Society Proceedings Symposium W, Volume: 525
  • "Nitric Oxide Rapid Thermal Nitridation of Thin Gate Oxides" 1997 Materials Research Society Proceedings Symposium F, Volume: 470
  • "A CMOS Technology for a Sub-5-ns 3.3V LVTTL 1-Mbit SRAM" 1995 Solid State Device Research Conference, Pages: 531 - 534 
  • "Effects and Prevention of Source/Drain Ion Implantation into the Polysilicon in a BiCMOS Technology" 1995 Electron Devices, IEE
  • "Study of C49-TiSi2 and C54-TiSi2 formation on doped polycrystalline silicon using in situ resistance measurements during annealing" 1994 Journal of Applied Physics, Volume: 76, Issue: 12
  • "Optimization of a High Volume 200-mm BiCMOS Manufacturing Line" 1993 Advanced Semiconductor Manufacturing Conference, Pages: 152 - 155 
  • "Yield Improvement for a 3.5-ns BiCMOS Technology in a 200mm Manufacturing Line" 1993 VLSI Technology, International Symposium on
  • "Sidewall Oxidation of Polycrystalline-Silicon Gate" 1989 Electron Device Letters, IEEE, Volume: 10, Issue: 9

 

 

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