Satyavolu Papa Rao

Satyavolu Papa Rao

Ph.D.
Satyavolu "Pops" Papa Rao
Adjunct Professor

Contact

Office Address:
NFE
Location
Albany
Faculty/Staff
Faculty
College
College of Nanoscale Science + Engineering

Degrees:

  • Ph.D., 1996, Materials Sci. & Eng., Massachusetts Institute of Technology, Cambridge, MA
  • B. Tech, 1988, Metallurgical Eng., Indian Institute of Technology, Madras, India

Areas of Research:

Papa Rao’s research interests are advanced nanofabrication techniques, and leveraging the capabilities of advanced 300mm processes and tools to address challenges in areas ranging from quantum computing devices through terahertz electronic devices to nano-biological structures. At the IBM TJ Watson Research Center, he co-led a research team that fabricated nanopore and nano-gap structures for DNA nucleotide recognition. Previously, he led a team that established robust processes for plated copper front-grid metallization for Si solar cells, with improved series resistance and lower shadowing. Since early 2015, he has led the effort at SUNY Poly to fabricate high performance superconducting qubits using 300mm fabrication processes, and is exploring the integration of single-flux-quantum logic circuits at the 300mm wafer scale. He is part of a team developing semiconductor and other applications of accelerated neutral atom beam technology utilizing the 300mm alpha tool installed by NPC at the SUNY Poly line. He is actively involved in working with the faculty of SUNY Polytechnic to identify, and pursue research funding for areas of strategic interest to the Institute.

Professional Background:

  • Vice President for Research, NY CREATES, Sept 2019 - present
  • Associate Vice President for Research, SUNY Polytechnic Institute, Jan 2017 – Sept 2019
  • Chief Technology Officer, SUNY Poly SEMATECH, Albany, NY, Aug 2015 - Dec 2016
  • Director of Process Technology, SEMATECH, Albany, NY, May 2014 - Aug 2015
  • Manager, IBM Research, Yorktown Heights, NY, Mid 2012 – May 2014
  • Research Staff Member, IBM Research, Yorktown Heights, NY, June 2007 - May 2014
  • Member Group Technical Staff, Texas Instruments, Dallas, TX, Mid 2004 – June 2007
  • Process Development Engineer, Texas Instruments, Dallas, TX, Apr 1996 – Mid 2004

Selected Recent Presentations/Publications:

  • “Fabrication of Superconducting Qubits with Low Variability at 300mm Wafer Scale”, (invited) S. Papa Rao et al, MRS Spring Symposium, April 17-21, 2017, Phoenix, AZ
  • “Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules”, C. Wang et al, Nat. Commun. 8, 14243 doi: 10.1038/ncomms14243 (2017)
  • “Epitaxial growth of GaSb and InAs fins on 300mm Si (001) by aspect ratio trapping”, T. Orzali et al, J. Appl. Phys. 120, 085308 (2016)
  • “Accelerated Neutral Atom Beam (ANAB) Processing for Atomic Layer Etch (ALE)”, E. Barth et al, Atomic Layer Etching 2016 Workshop, July 24-27, 2016, Dublin, Ireland. 
  • “Ultra Low-K Materials and Chemical Mechanical Planarization” chapter, J. Nalaskowski, S.S. Papa Rao, in “Advances in Chemical Mechanical Planarization (CMP)”, Woodhead Publishing, 2016.
  • “GaAs on Si epitaxy by aspect ratio trapping: Analysis and reduction of defects propagating along the trench direction”, T. Orzali et al, J. Appl. Phys. 118, 105307 (2015).
  • “Technology options to reduce contact resistance in nanoscale III-V MOSFETs”, R.T.P. Lee et al, ECS Transactions, 66 (4), 125-134, 2015.
  • “Light Assisted Electrodeposition and Silicidation of Ni for Silicon Photovoltaic Cell Metallization”, Q. Huang, S.S. Papa Rao, K. Fisher, ECS Journal of Solid State Science and Technology, Vol 4(8), 2015, Q75-Q82.
  • “Fabrication of sub-20 nm Nanopore Arrays in Membranes with Embedded Metal Electrodes at Wafer Scales”, J. Bai et al, Nanoscale 06/2014, 6(15) 8900-8906. 
  • “Challenges in Fabrication of Nanoscale devices for DNA Base Sensing” (invited), S.S. Papa Rao et al, American Vacuum Society 60th International Symposium, Long Beach, CA, Oct 27-Nov 1, 2013
  • “200 mm Wafer-Scale Integration of Sub-20 nm Sacrificial Nanofluidic Channels for Manipulating and Imaging Single DNA Molecules”, C. Wang et al, International Electron Devices Meeting, December 2013.
  • “Nondestructive Defect Characterization of Saw-Damage-etched Multicrystalline Silicon wafers using Scanning Electron Acoustic Microscopy”, L. Meng, S.S. Papa Rao, C.S. Bhatia, S.E. Steen, A.G. Street, J.C.H. Phang, IEEE Journal of Photovoltaics, 3, 370-374, (2013)
  • “Advanced Interconnects and Chemical Mechanical Planarization for Micro- and Nanoelectronics”, MRS Proceedings Volume 1249, Editors: J.W. Bartha, C.L. Borst, D. DeNardis, H. Kim, A. Naeemi, A. Nelson, S.S. Papa Rao, H.W. Ro, D. Toma
  • “Effects of Chemical Mechanical Polishing on a porous SiCOH dielectric", S. Gates, et al. Microelectronic Engineering, Vol 91 (2012) p82-89
  • “Thermal Stability of Copper Contact Metallization Using Ru-containing Liner”, S-C Seo et al, Electrochemical and Solid State Letters, 14 (2011) 5 H187-H190
  • “Development And Characterization of Advanced Process Technologies for the Fabrication of Crystalline-Si Solar Cells”, S.S. Papa Rao et al, 35th IEEE Photovoltaic Specialists Conference, Hawaii. June 20-26, 2010
  • “Reducing Time Dependent Line-to-Line Leakage Following Post CMP Clean”, D.F. Canaperi et al, MRS Spring 2010 Symposium, San Francisco, CA, April 6-10, 2010
  • “Processing and Moisture Effects on TDDB for Cu/ULK BEOL Structures”, E.G. Liniger et al, 27th Advanced Metallization Conference, Albany, NY, Oct 5-7, 2010
  • “Processing and Moisture Effects on TDDB for Cu/ULK BEOL Structures”, E.G. Liniger et al, Microelectronic Engineering, Vol 92 (2012), p130-133.

Selected US Patents:

  • Biological nanostructures: 9,097,698; 9,012,329; 9,128,078 (nanogap devices); 9,168,717 (solid-state nanopore device), 9,013,010 (nanopore-based sensor)
  • Photovoltaic device and processing: 8,440,494 (texturing of crystalline Si); 8,865,502 (plated back surface field); 8,962,374 (titania-based antireflection coating)
  • Integrated capacitors/inductors: 7,153,706 (ferroelectric capacitor with planarization); 7,118,925 (ferromagnetic inductor core and capacitor electrode); 6,919,233; 6,898;068; 6,803,641; 6,924,208; 7,015,093; 7,115,467 (all various aspects of MIMcap fabrication, integration and layout)
  • IC interconnect metallization unit-processes: 7,148,140 (Plate-anneal-plate); 7,037,837 (nucleation/seed layer); 6,900,127 (plateable barriers); 6,579,798 (CMP defect control)
  • Metrology/defect patents: 6,864,108 (wafer temperature measurement); 6,834,117 (X-ray defect detection)
    and other patents on liner stress modification for P and NMOS transistors, surface defect elimination using directed beams, etc.

Awards:

  • IBM Research Award for development of CMP for advanced CMOS nodes, 2014
  • Elected to Texas Instruments’ Technical Ladder, ”Member, Group Technical Staff”, 2004
  • Intel Foundation Graduate Fellowship, Mentor: Dr. E. Meieran (Intel Fellow), 1991- 1992.
  • Institute Merit Prize, IIT-Madras: student with best academic record in Metallurgical Eng.
  • National Science Talent Scholarship, The Government of India, 1982-1988

 

 

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