Professional Background

• Director of CMP, Thermal, Cleans Division for G450C, College of Nanoscale Science and Engineering (2015-present)
• Manager of CMP, Thermal, Cleans Process Engineering for G450C, College of Nanoscale Science and Engineering (2014-2015)
• Senior Thermal Process Engineer, G450C, College of Nanoscale Science and Engineering (2012-2014)
• Senior Process Development Engineer (FEOL), College of Nanoscale Science and Engineering (2009-2012)
• Lithography Process Engineering Manager, Qimonda NA (2007-2009)
• Process Engineering & Engineering Manager Positions, IBM Microelectronics (2001-2007)

Education

• BSE, Electrical Engineering, University of Michigan, College of Engineering, Ann Arbor, MI, 2000.

Responsibilities

As the Director of the CMP, Thermal, Cleans Division for G450C, Mr. França and his team are responsible for the configuration, installation, start-up, acceptance, process development & qualification, maturity assessments, and continuous hardware & process improvements of the 450mm CMP, thermal, and cleans equipment. 

Issued Patents

• Real Time Profiling and Conditioning of Chemical Mechanical Polish Pads Patent No. 6,343,974; Date of Patent - February 5, 2002.
• Light Energy Cleaning of Polish Pads Patent No. 6,217,422; Date of Patent - April 17, 2001.
• Method and Apparatus for Ozone Generation and Surface Treatment Patent No. 6,178,973; Date of Patent - January 30, 2001.

Conference Publications and Presentations

• Effects of HCl on the Growth of Epitaxial Ge (ECS Trans., 2013, Vol. 50, Issue 9: pp. 395-398.)
• Non Planar Non Si CMOS – Challenges and Opportunities (ECS Trans. 2013, Vol.50, Issue 9, pp. 669 -672.)
• Strained SiGe and Si FinFETs for High Performance Logic With SiGe/Si Stack On SOI (Electron Devices Meeting (IEDM), 2010 IEEE International, January 28, 2011, pp. 34.2.1 – 34.2.4.)
• Enhanced Performance in SOI FinFETs With Low Series Resistance By Aluminum Implant as a Solution Beyond 22nm Node (VLSI Technology 2010 Symposium, August 23, 2010, pp. 17-18.)
• A Yield Enhancement Methodology for Launching New Technologies Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium, September 13, 2005, pp. 491- 494.