Frank Tolic

Frank Tolic

Frank Tolic
Associate Vice President for Business, Wafer Processing

Contact

Phone Number:
518-956-7221
Office Address:
NFE
4217
Faculty/Staff
Staff
Department
Business Office

Professional Background

  • Global Account Executive, SVTC Technologies, LLC, 2011-2012, Austin TX
  • Global Business Development Manager, SVTC Technologies, LLC, 2008 – 2011, Austin TX
  • Global Business Unit Manager, ATDF, Inc., 2004 -2008, Austin TX
  • Product Manager, International SEMATECH, 2000-2004, Austin TX
  • Senior Device Integration Engineer, FEOL/BEOL, Motorola’s Advanced Products Research and Development Laboratory ( APRDL), 1995-2000, Austin TX
  • Production and Quality Engineer, Motorola’s Automotive and Industrial Electronics Product Group, 1993-1995, Seguin TX
  • Manufacturing Engineer, Ford Motor Co., 1991-1992, Plymouth MI
  • Engineering Co-Op, GM Saturn Corporation, 1988-1991, Troy MI & Springhill TN

Responsibilities

As Associate Vice President for Business, Wafer Processing, Mr. Tolic is responsible for managing the overall business and satisfaction of companies currently utilizing or looking to utilize the semiconductor processing capabilities at CNSE.

He is also responsible for business development with companies looking to engage with CNSE faculty research, analytical labs, and other long term strategic business partnerships. In his role, Mr. Tolic coordinates technical marketing functions, and joint customer/technical related seminars at CNSE.

Mr. Tolic's focus on customer satisfaction involves ensuring a positive customer relationship by working with the customer and CNSE staff to develop new and unique methods to enhance the customer’s experience with all levels of CNSE, and ensure continuous improvement.

Areas of Specialty

  • Increasing and improving customer satisfaction
  • Maximizing customer’s ROI of R&D dollars
  • Expanding market share for customers and companies own products
  • Technical sales and marketing of R&D

Education

  • B.S. (Electrical Engineering and Mechanical Engineering), Lawrence Technological University, Southfield, MI, 1991

Awards

  • CEO Award – SVTC, February 2012
  • Supplier Achievement Award - Cabot Microelectronics, September 2011
  • Outstanding Contribution Award - International SEMATECH, August 2003
  • Personal Achievement Award – Motorola, November 1994
  • Navistar Quality Award – Navistar, July 1994
  • Honda Quality Award - Honda Motors, November 1993

Publications and Talks

“Continued growth and benefits of CMP development and production outsourcing” 
- Frank Tolic, SVTC, CMPUG Proceedings, Business Aspects of CMP, Semicon West, July 2009

“Novel CMP Pad Design for Sub 45nm CMP Processes” R. Carpio1, J. Pham1, F. Tolic1, S. Hymes2, and R. Bajaj2; 1ATDF, 2SemiQuest Inc. 2006 International Conference on Planarization/CMP Technology (2006 ICPT) 
October 2006 

“Pattern Density Distribution Effect on Copper CMP” G. Wu, S. Kirtley, and T. West, Thomas West, Inc.; F. Tolic, R. Carpio, J. Pham, and R. Santana, ATDF. 2006 International Conference on Planarization/CMP Technology (2006 ICPT) October 2006 

“CMP Pad Design for Ultra-Low-k Compatible Copper CMP Process” by R. Carpio, J. Pham and F. Tolic; ATDF; Austin, TX; and S. Hymes, R. Bajaj; SEMIQUEST. Twenty Third International VLSI/ULSI Multilevel Interconnection Conference, September 2006

"Study of Copper CMP Effect on Copper Damascene Nano Structures Using Mask 454" Ron Carpio and Frank Tolic, ATDF, and Paul Lefevre, Fujimi Corporation. Symposium on Chemical-Mechanical Planarization CAMP, August 2006 

“Evaluating the use of single-wafer wet cleans with organic spin-on dielectric materials” Leo Archer, SEZ America, Joost Waeterloos and Michael Simmonds, Dow Chemical, Frank Tolic, International Sematech, and Ketan Itchhaporia. Micromagazine, June, 2004

“A Versatile 0.13 μm CMOS Platform Technology Supporting High Performance and Low Power Applications” A.H. Perera, B. Smith, N. Cave, M. Sureddin, S. Chheda, R. Singh, M. Celik, S.-C. Song, D. Wu, A. Sultan, J. Chang, R. Islam, K.C. Yu, R. Fox, S. Park, F. Tolic, C. Simpson, S., Motorola DigitalDNA Laboratories and AMD. IEDM, San Francisco, December 2000

“A High Performance 3.97um2 CMOS SRAM Technology Using Self-Aligned Local Interconnect and Copper Interconnect Metallization” M. Woo, M. Bhat, M. Craig, P. Kenkare, X. Wang, F. Tolic, H. Chuang, S. Parihar, J. J. Schmidt, L. Terpolilli, et al., Motorola. 1998 Symposium on VLSI Technology

 

 

 

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