Hyuncher Chong

Hyuncher Chong

SUNY Polytechnic Institute
Senior Process Development Engineer

Contact

Phone Number:
518-956-7010
Office Address:
NFX
449
Location
Albany
Faculty/Staff
Staff

Professional Background

  • Senior Process Development Engineer - College of Nanoscale Science and Engineering, University at Albany

  • Member of Technical Staff - Applied Materials Inc., College of Nanoscale Science and Engineering, Albany, NY, 2006 - 2009
  • Member of Technical Staff - Applied Materials Inc., Hopewell Junction, NY, 1999 - 2005
  • Intel Account Technologist - Applied Materials Inc., Physical Vapor Deposition Division, Santa Clara, California, 1994 - 1998
  • Member of Technical Staff - Plasma & Materials Technologies, Chatsworth, California, 1992 - 1994
  • Process Engineer - Materials Research Corporation, Orangeburg, New York, 1988 - 1992

Education

  • Graduate Studies in Material Science, Stevens Institute of Technology, Hoboken, NJ
  • B.S. (Electrical Engineering), Rutgers, The State University of New Jersey, Piscataway, NJ

Responsibilities

As a Process Development Engineer, Mr. Chong is responsible for multiple aspects of joint development activities with CNSE's ever growing corporate partnerships. Mr. Chong works to ensure that the partners challenging integration schemes are accomplished using novel dielectric and metal films for both BEOL / FEOL processing solutions.

Mr. Chong is the primary contact for PECVD dielectric film depositions, advanced low K SiCOH , STI gap fill, Advance Patterning Film, PVD liners / Cu seed, Silicide, and metal gate electrode process. He supports development activities for conventional planer CMOS, non-planer FinFET devices. He also supports advanced memory applications, with top / bottom electrode materials and unique metal oxide dielectric films for reliability improvement.

Conference Publications and Presentations

  • Integration of HARP into STI Process Flow: STI Liner Plasma Treatment and Post HARP Deposition RTA. ET conference, May 2007
  • ALD/PVD barrier reduces RC and improves reliability. Semiconductor International, June, 2004
  • Demonstration of HSiON/MeNx Tunable Work Function High-k/Metal Gate MOSCAP for LSTP/DRAM Peripheral FET to Achieve Vet(n-p) = 500 mV and Equivalent Oxide Thickness (EOT) <1.1nm 
  • Process and Plasma density modeling & Characterization of Helicon Plasma Source for Reactive Ion Etching Process. July, 1993
  • Physical Vapor Deposition Process Class - One week course developed and taught Applied Global University, June 1996

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