Professional Background

• Process Integration Manager, College of Nanoscale Science and Engineering
• Process Engineering Failure Analysis Facility, College of Nanoscale Science and Engineering
• Process Development for advanced CMOS, Motorola Semiconductor at IMEC Belgium
• Reliability and Failure Analysis Lab, Motorola Semiconductor

Education

• Ph.D. (Chem Engr), University of New Mexico
• M.S. (Chem Engr), Colorado State University 
• B.Tech. (Chem Engr), IIT Bombay, India

Responsibilities

With his extensive background in advanced CMOS processing as well as physical/electrical characterization, Dr. Kaushik manages multiple technology development partner projects in the CNSE 300mm fab. The integration team, working with the unit process development team and fab Ops team, supports current and advanced technology offerings.

Awards + Patents

• Invited Speaker at Atomic Layer Deposition Conference, Seoul Korea, 2006
• Session Chair at MRS Materials Research Society Fall Meeting Boston, 2003
• Invited Speaker at Massachusetts Institute of Technology (MIT) VLSI Seminar Series, 2001
• Invited Tutorial at IRPS on Analytical Electron Microscopy of Semiconductor Devices, 1994
• Best Paper Award at International Society of Testing and Failure Analysis Meeting, 1993
• Outstanding Graduate Student Award, University of New Mexico, 1989
• Presidential Student Award of Microscopy Society of America, Milwaukee 1988
• United States Patent 5,236,852 Method for contacting a semiconductor device 1993
• United States Patent 5,712,177 Method for forming a reverse dielectric stack 1998
• United States Patent 6,184,072 Process for forming a high-K gate dielectric 2001
• United States Patent 6,448,192 Method for forming a high dielectric constant material 2002
• United States Patent 6,518,106 Semiconductor device and a method therefor 2003
• United States Patent 6,518,634 Strontium nitride or strontium oxynitride gate dielectric 2003
• United States Patent 6,541,280 High K dielectric film 2003
• United States Patent 7,622,387 Gate electrode silicidation process 2009

Selected Publications + Presentations

‘Estimation of fixed charge densities in hafnium-silicate gate dielectrics', Kaushik, V.S.; O'Sullivan, B.J.; Pourtois, G.; et al. Electron Devices, IEEE Transactions on Volume 53,  Issue 10,  Oct. 2006 Page(s):2627 - 2633

‘Device performance of transistors with high-/spl kappa/ dielectrics using cross-wafer-scaled interface-layer thickness'  O'Sullivan, B.J.; Kaushik, V.S.; Ragnarsson, L.-A.; et al. Electron Device Letters, IEEE Volume 27,  Issue 7,  July 2006 Page(s):546 - 548

Engineering Of Ald Hf-Silicates For Low Standby Power Applications"  (Invited Paper) V.Kaushik, W.DeWeerd, E.Rohr, S.Hyun, et al., presented at the 2006 Atomic Layer Deposition Conference, Seoul Korea, July 24-26 2006

Observation And Characterization Of Defects In Hfo2 High-K Gate Dielectric Layers, Kaushik V, Claes M, Delabie A, Van Elshocht S, Richard O, et al. Microelectronics Reliability 45 (5-6): 798-801 May-Jun 2005 

Compatibility Of Polysilicon With Hfo2-Based Gate Dielectrics For CMOS Applications,V.S. Kaushik, S.DeGendt, M.Caymax, S.V.Elshocht, et al. Presented and published in the Proceedings of the Electrochemical Society Spring 2003 Meeting Paris April 27 2003

Influence of Defects on Compatibility and Yield of the HfO2-PolySilicon Gate Stack for CMOS Integration, V.S. Kaushik, S.DeGendt, R.Carter et al. Presented and published in the Proceedings of the Materials Research Society Fall 2002 Meeting Boston Dec 2-6 2002 Vol 745

Progress and Integration Challenges of the Metal Oxide development for CMOS Gate Dielectric application (Invited Paper) B-Y.Nguyen, V.Kaushik, J.Schaeffer, A.Barr et al. 8th International Conference on Electronic Materials (IUMRS-ICEM 2002), China June 2002

Pulling the Rug from under- The Move to High-K, Invited Seminar at the MIT Electrical Engineering and Computer Science, MTL VLSI Seminar Series, V. Kaushik, May, 2001

Device Characteristics Of Crystalline Epitaxial Oxides On Silicon, Kaushik, V.; Eisenbeiser, K.; Nguyen, B.-Y.; et al. Invited Paper at the 58^th Device Research Conference. Conference Digest p.17-20 2000

HRTEM As A Metrology Tool In ULSI Processing, Kaushik, V.S.; Prabhu, L.; Anderson, A.; Conner, J., AIP Conference Proceedings no.449 p.854-6 1998

An Analytical Study Of A Novel And New Failure Mechanism Observed In A High Density CMOS ULSI Device, Pyle, R.E.; Kaushik, V.; Laberge, P.; Morris, S.; Martin, L.; et al. ISTFA '95. 21st International Symposium for Testing and Failure Analysis p.129-34 1995

Electron Microscopy Study Of The Influence Of The Adhesion Layer For Pt Electrode On The Microstructure Of Sol-Gel Crystallized PZT, Kaushik, V.; Maniar, P.; Campbell, A.; et al. Ferroelectric Thin Films III Symposium p.209-14 1993

Microstructure Of Pores In N/Sup +/ Silicon, Kaushik, V.S.; Datye, A.K.; Tsao, S.S.; Guilinger, T.R.; Kelly, M.J., Materials Letters vol.1, no.3-4 p.109-14 May 1991

Coherent Precipitation of Silicon Nitride in Silicon, V.Kaushik, A.Datye, D.Kendall, B.Martinez and D.Myers, Applied Physics Letters, 52 (21) p1782 1988.