Silicon Semiconductor: Graphene, Waiting in the Semiconductor
Wings

Silicon Semiconductor: Graphene, Waiting in the Semiconductor
Wings

Published:
Thursday, March 19, 2015 - 14:05
SUNY Poly News Logo

I wanted to share with you the following article that was published by Silicon Semiconductor:

“…Researchers at the College of Nanoscale Science and Engineering at SUNY Polytechnic Institute used just this method in their recent work on “Processing of graphene on 300mm Si wafers in a state-of-the-art CMOS fabrication facility.”

The CNSE team grew graphene films on copper foil substrates, placed thermal- release tape as the handle substrate, then released the copper foil using wet etch. The graphene and its handle substrate (the tape) were then placed on a 300mm bare Si wafer, or on an SiO2-capped silicon wafer, which was then heated to remove the thermal-release tape, resulting in a 300mm silicon wafer covered with graphene, ready for subsequent processing…"

 

Silicon Semiconductor: Graphene, Waiting in the Semiconductor Wings

It’s time to take a look at an old friend in semiconductor fabrication, carbon, in a new guise, that of grapheme.  

By Paul Werbaneth, Contributing Editor, 3D InCites

Wednesday 18th March 2015

Graphene, composed of pure carbon atoms arranged as a one atom-thick sheet, is one of the thinnest, strongest materials created, and has great potential to change the way that electronic devices, spintronic devices, photonic and optoelectronic devices, and MEMS and sensors are made.

Graphene may also be the key to enabling and commercializing flexible displays for smartphones and wearables, among other applications coming right around the corner.  [Source: Wikipedia.]

752445852394830.jpg

In the review article “Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems” recently published in in the Royal Society of Chemistry journal Nanoscale, the impressive number of authors (more than 60) “present the science and technology roadmap for graphene, … targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society.”

This graphene science and technology roadmap was developed within the framework of the European Graphene Flagship, which says about itself this: “The Graphene Flagship is the EU’s biggest ever research initiative. With a budget of €1 billion, it represents a new form of joint, coordinated research on an unprecedented scale. The Graphene Flagship is tasked with bringing together academic and industrial researchers to take graphene from the realm of academic laboratories into European society in the space of 10 years, thus generating economic growth, new jobs and new opportunities.”

The Graphene Flagship science and technology effort, reduced to just two slides, is this:

846326047455068.jpg

[Source: Nanoscale, 2015.]

From a Semiconductor Industry perspective, there is much to like about where the Graphene Flagship effort is headed; flexible electronics and flexible displays are two particularly exciting areas of development.

Graphene Production Graphene films can be manufactured in multiple ways, as illustrated by this figure from the previously cited work in Nanoscale:

576466118298170.jpg Graphene Production from Nanoscale [Source: Nanoscale.]

Large area graphene films grown by chemical vapour deposition (CVD) on catalytic surfaces such as copper, platinum or germanium require high temperatures, roughly 1000°C, and use a gaseous source of carbon, for example methane, as the precursor.

With this CVD-on-substrate method, the graphene produced has to be mechanically transferred from the catalytic growth surface to the desired substrate, which is typically accomplished with the help of thin “handle” films.

Researchers at the College of Nanoscale Science and Engineering at SUNY Polytechnic Institute used just this method in their recent work on “Processing of graphene on 300mm Si wafers in a state-of-the-art CMOS fabrication facility.”

The CNSE team grew graphene films on copper foil substrates, placed thermal- release tape as the handle substrate, then released the copper foil using wet etch. The graphene and its handle substrate (the tape) were then placed on a 300mm bare Si wafer, or on an SiO2-capped silicon wafer, which was then heated to remove the thermal-release tape, resulting in a 300mm silicon wafer covered with graphene, ready for subsequent processing.

This is not yet the “large scale and cost-effective production methods” we need for graphene in semiconductor manufacturing, but work on that is being actively pursued in Europe, in Albany, and in Texas, and abroad, at NASCENT, the Nanomanufacturing Systems for mobile Computing and Energy Technologies partnership, whose members include The University of Texas at Austin, The University of New Mexico, The University of California at Berkeley, Indian Institute of Science, and Seoul National University.

The Trouble With Graphene Transistors Zero band-gap. That’s the major strike against using graphene in transistor applications, especially when graphene is considered as a potential replacement for silicon in order to implement flexible electronic devices in hand-helds and wearables, for example. Zero band-gap results in low ON/IOFF in graphene Field Effect Transistors, due to a non-zero off state drain current in the GFETs, which leads to undesirably large static power dissipation.

That’s battery drain, and that’s a no-no. Therefore, engineering a way to a non-zero band-gap in graphene without compromising any of its other outstanding properties in the process is currently one of the most active research areas being pursued for graphene as an electronics material. Early results are promising, but more work is required.

Graphene, Flexible Displays, and Kirigami Commercially, looking close-in, the two main characteristics of graphene that will gain it traction as a disruptive technology in the electronics industry are its flexibility and its transparency. Deploying graphene in flexible substrate applications or in flexible displays makes it the ideal material in the transition from rigid to flexible electronics, one flavor of the many “More than Moore” technologies being actively explored by the industry.

Samsung has a formidable position in graphene-related IP, with more than 400 patents filed to date, according to John Lang at the LCS Business School, and word on the street is that Samsung is enthusiastically working on foldable touch screen displays for smartphones, wearables, and hand-held devices, with commercial products expected to be on the market sometime in 2015 - 2016.

Nokia, a few years ago, presented concepts for an absolutely beautiful product, the Morph, a flexible, configurable smartphone.

875875263914725.jpg

[Source: Nokia.]

In its work with concepts like the Morph, Nokia said it is looking to explore “nanoscale technologies that will potentially create a world of radically different devices that open up an entirely new spectrum of possibilities.”

Graphene has capabilities that silicon doesn’t, and there is much to explore and understand. One important graphene explorer is Prof. Paul L. McEuen, Cornell University, the John A. Newman Professor of Physical Science, and the Director, LAASP and Kavli Institute at Cornell for Nanoscale Science, who will be presenting a tutorial on “The Science, Technology and Art of Graphene” during the SEMI Advanced Semiconductor Manufacturing Conference 2015. In his talk, Prof. McEuen will give a biased (he says) overview of the science and technology of the 2D material graphene; his topics will include characterization of graphene in electronic and mechanical devices, including stretchable electronics based on the Japanese art of kirigami (cutting and folding paper).

About ASMC 2015 ASMC 2015 features two dedicated tutorials this year, along with three days of insightful technical presentations, keynotes talks from leaders in the semiconductor industry, and a panel discussion on “Semiconductor Manufacturing: Keeping the Silicon Magic Alive,” with panelists from DARPA, GE Global Research, Lam Research and Rochester Institute of Technology.

ASMC 2015 opens with a welcome reception on Sunday 03 May 2015 in Saratoga Springs, NY, and concludes with a keynote talk by Robert Maire, Semiconductor Advisors, on Wednesday afternoon the 6th of May.  Professors McEuen’s graphene tutorial will be held on Monday afternoon, the 4th of May, at 3:50pm.

Registration for ASMC 2015 is available at www.semi.org/asmc2015.  For more information, please contact Margaret Kindling, SEMI, at mkindling@semi.org or phone her at 1.202.393.5552. Qualified members of the media should contact Deborah Geiger (SEMI Public Relations) at dgeiger@semi.org for media registration information.

Other
News